Several AES Variants under VHDL language In FPGA
نویسندگان
چکیده
This paper provides four different architectures for encrypting and decrypting 128 bit information via the AES. The encryption algorithm includes the Key Expansion module which generates Key for all iterations on the fly, Double AEStwo-key triple AES, AESX and AES-EXE. These architectures are implemented and studied in Altera Cyclone III and STRATIX Family devices.
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ورودعنوان ژورنال:
- CoRR
دوره abs/1210.4962 شماره
صفحات -
تاریخ انتشار 2012